Position: Synthesis Engineer
Department: Delivery
Job level: Technical Lead
Direct report: Manager
Responsibility:
- Responsible for all front-end integration activities like Lint, CDC, Synthesis, LEC, Low Power and UPF, formal verification, STA and ECO implementation
- Do Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power. Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them
- Do Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures
- Develop Timing Constraints for RTL-Synthesis and STA-Signoff for the blocks and the top – level including SOC. Analyze the inter-block timing and come up with IO budgets for the various partition blocks
- Implement, enhance and maintain Synthesis, STA scripts and various automation flows
- Work closely with logic design and PnR engineers on logic, timing, power and physical issues
Requirements:
- At least 8+ years of Synthesis engineering experience
- High level of work execution on complex technical projects
- Coaching and mentoring to build the next level of technical reviewers and technical leaders
- Supporting root cause analyses and improvement actions
- Conduct technical reviews / deliverable reviews and monitor technical health of projects
- Support hiring by conducting technical interviews and training other technical interviewers
Work Location: HCM, Da Nang
