Position: Synthesis Engineer
Department: Delivery
Job Level: Lead/Sr.Lead
Direct report: Manager
Responsibility:
– Responsible for all front-end integration activities like Lint, CDC, Synthesis, LEC, Low Power and UPF, formal verification, STA and ECO implementation
– Do Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power. Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them
– Do Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures
– Develop Timing Constraints for RTL-Synthesis and STA-Signoff for the blocks and the top-level including SOC. Analyze the inter-block timing and come up with IO budgets for the various partition blocks
– Implement, enhance and maintain Synthesis, STA scripts and various automation flows
– Work closely with logic design and PnR engineers on logic, timing, power and physical issues
Qualifications:
– 6+ years of Synthesis engineering experience
– Familiarity of ASIC design flow (FrontEnd, DFT, PnR)
– Hands-on experiences in front-end implementation tasks such as synthesis, constraint developing, timing, area/power analysis, linting, and logic equivalence checks
– Hands on experiences in EDA implementation tools for logic synthesis (DC/FC, Genus), RTL/Netlist Check (SpyGlass Lint), LEC (Formality, Conformal), Multi Voltage
– Verification (VC LP, Conformal LP), STA (PrimeTime, Tempus)
– Experience in multi-clock and multi-power domain designs
– Scripting and programming experience using Perl/Python, TCL, etc.
– Knowledge of RTL coding using Verilog/System Verilog or Physical Design is a plus
– On-time completion of work
– High quality execution of high complexity work
– Support customer presentations exemplifying our capability
– Help answer team members’ technical questions
– Quest Global standard work – creation and maintenance and support
– Participate in technical reviews (possibly sign off on/conduct technical reviews). Peer
Reviews
– Mentor junior team member (Band 1E, 1D, 1C) to develop capability
Work Location
• Room 901, Nguyen Lam Building, 133 Duong Ba Trac Street, Rach Ong Ward, District 8, Ho Chi Minh City, Vietnam
Working hours
• Flexible. From 9:00 AM to 6:00 PM.
