Responsibility:
– Responsible for the full physical design cycle from Synthesis to GDSII
– Perform tasks like Synthesis, floor-planning, placement, CTS, routing, and timing analysis
– Perform the signoff check like: STA/ EMIR (IR, DvD, P-EM, S-EM)/PV(LVS/ANT/DRC/DFM) /Low power check … tape-out procedures
– Ensure the design meets performance, power, and area constraints
– Utilize Electronic Design Automation (EDA) tools for design, simulation, and verification
– Work closely with stakeholders like: Design team, constraint team, DFT team, DV team, IP team to ensure the physical layout meets design specifications
– Perform physical verifications such as layout versus schematic (LVS) and design rule checking (DRC)
– Conduct parasitic extraction and analysis to optimize the performance of the IC
– Resolve design and flow issues related to physical design, identify potential solutions, and drive execution
– Optimize designs for power, area, and performance
– Stay up to date with the latest technology trends (7nm/5nm/3nm and beyond), industry standards, and EDA tools
– Conduct logic synthesis, floor planning, power and clock distribution, timing optimization, signal integrity and place and route
– Work closely with team members to resolve design and flow
Requirements:
– At least 8+ years of PD engineering experience
– Plan, allocate resources, assign tasks and direct activities of the team to meet aggressive schedules and achieve milestone criteria
– Identify and analyze progress gating issues and implement plans, tasks, and solutions to quickly resolve
– Propose creative, innovative methodology and process initiatives to consistently improve efficiency and quality of deliverables
– Provide coaching, guidance and feedback to direct reports on career development, performance, and productivity issues
– Build a strong and technically vital organization. Cultivate and reinforce appropriate group values, norms and behaviors
– Excellent analytical, problem solving and debugging skills with strong interest in semiconductor technology
– Require having at least 3+ years’ experience on managing and leading teams in chip design industries
– Individual who consistently looks for ways to do things more efficiently while upholding quality
– Passionate in solving problems, ability to synthesize data and translate into data driven proposals and decisions
Work Location
•Phòng 901, Tòa nhà Nguyễn Lâm, 133 Dương Bá Trạc, Phường Rạch Ông, Quận 8, Thành phố Hồ Chí Minh, Việt Nam
Working hours
• Flexible. From 9:00 AM to 6:00 PM.
