Responsibility:
– Responsible for the full physical design cycle from Synthesis to GDSII
– Perform tasks like Synthesis, floor-planning, placement, CTS, routing, and timing analysis
– Perform the signoff check like: STA/ EMIR (IR, DvD, P-EM, S-EM)/PV(LVS/ANT/DRC/DFM) /Low power check … tape-out procedures
– Ensure the design meets performance, power, and area constraints
– Utilize Electronic Design Automation (EDA) tools for design, simulation, and verification
– Work closely with stakeholders like: Design team, constraint team, DFT team, DV team,IP team to ensure the physical layout meets design specifications
– Perform physical verifications such as layout versus schematic (LVS) and design rule checking (DRC)
– Conduct parasitic extraction and analysis to optimize the performance of the IC
– Resolve design and flow issues related to physical design, identify potential solutions, and drive execution
– Optimize designs for power, area, and performance
– Stay up to date with the latest technology trends (7nm/5nm/3nm and beyond), industry standards, and EDA tools
– Conduct logic synthesis, floor planning, power and clock distribution, timing optimization, signal integrity and place and route
– Work closely with team members to resolve design and flow
Requirements:
– Leading a team < 10HC
– Communicate with customers to make clear all requirements and guarantee the output of the team
– Escalate issue with solution and follow up until the issue is closed
– Proactively share and improve knowledge with other colleagues
– 6+ years of experience in Physical Design
– Advance analysis/fixing skill (timing/congestion/signoff items), multitask handling
– Ability to report directly to customers
– Experience in leading a team and training a new member
– Actively confirm/ask questions and no assuming
Work Location
•Phòng 901, Tòa nhà Nguyễn Lâm, 133 Dương Bá Trạc, Phường Rạch Ông, Quận 8, Thành phố Hồ Chí Minh, Việt Nam
Working hours
• Flexible. From 9:00 AM to 6:00 PM.
