Responsibility:
Conduct DFT Engineering Tasks: DFT Audit/Scan Logic/MBIST Logic/BSCAN Logic Insertion
– Responsible for implementing the Hardware Design-for-Test (DFT) features that support
ATE, in-system test, debug and diagnostics needs of the design
– Responsible for development of innovative DFT IP in collaboration with cross-functional
teams, and play a key role in full chip design integration with the testability features
integrated in RTL
– Work closely with the design/design-verification and physical design teams to enable the
integration and validation of the Test logic in all phases of the design, and back-end
implementation flow
– Analyze timing report and suggest for the solution
– Skillful in gate-level simulations with and without timing annotations
– Diagnose and analyze data logs during silicon bring-up phase to finalize prototype patterns
– Be responsible for Innovative Hardware DFT for new silicon device models, bare die &
stacked die- driving re-usable test and debug strategies
Requirements:
– At least 8+ years of DFT engineering experience
– Strong leadership skills
– Be able to work on two or more projects simultaneously
– Strong support for team members
– Be able to mentor and train junior engineers in the overall process
– Knowledge of industry standards for DFT and Design tools
– Experience with whole-chip DFT with different flows: fully Tessent Shell flow, hybrid
flow (mixed vendor tools) …
– Experience with coverage debugging to achieve high Stuck-At coverage (99.5%)
– Depth experience in stuck at, transition delay, path delay, etc. coverage loss analysis and
identifying solutions to improve test coverage
Location
-Phòng 901, Tòa nhà Nguyễn Lâm, 133 Dương Bá Trạc, Phường Rạch Ông, Quận 8, Thành phố Hồ Chí Minh, Việt Nam
Working hours
-Flexible. From 9:00 AM to 6:00 PM.
